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ISL97671
Output Channel Mask/Fault Readout
Register (0x09)
This register can be read or write; the bit position corresponds to
the channel. For example, Bit 0 corresponds to Ch0 and bit
5corresponds to Ch5 and so on. Writing data to this register, it
enables the channels of interest. When reading data from this
Phase Shift Control Register (0x0A)
The Phase Shift Control register is used to set phase delay
between each channels. When bit 7 is set high, the phase delay
is set by the number of channels enabled and the PWM
frequency. Refer to Figures 4 and 5, the delay time is defined by
Equation 17:
register, any disabled channel and any faulted out channel will
read as 0. This allows the user to determine which channel is
t D1 = ( t FPWM ? N )
(EQ. 17)
t PD = ( PS < 6 , 0 > xt FPWM ? ( 255 ) )
faulty and optionally not enabling it in order to allow the rest of
the system to continue to function. Additionally, a faulted out
channel can be disabled and re-enabled in order to allow a retry
for any faulty channel without having to power-down the other
channels.
The bit assignment is shown in Figure 36. The default for
Register 0x09 is 0x3F.
where N is the number of channels enabled, and t FPWM is the
period of the PWM cycle. When bit 7 is set low, the phase delay is
set by bits 6 to 0 and the PWM frequency. Referencing Figure 24,
the programmable delay time is defined by Equation 18:
(EQ. 18)
where PS is an integer from 0 to 127, and t FPWM is the period of
the PWM cycle. By default, all the register bits are set low, which
sets zero delay between each channel. Note that the user should
not program the register to give more than one period of the
PWM cycle delay between the first and last enabled channels.
REGISTER 0x09
OUTPUT CHANNEL REGISTER
Reserved
Bit 7 (R/W)
Reserved
Bit 6 (R/W)
CH5
Bit 5 (R/W)
CH4
Bit 4 (R/W)
CH3
Bit 3 (R/W)
CH2
Bit 2 (R/W)
CH1
Bit 1 (R/W)
CH0
Bit 0 (R/W)
BIT ASSIGNMENT
CH[5..0]
REGISTER 0x0A
BIT FIELD DEFINITIONS
CH5 = Channel 5, CH4 = Channel 4 and so on
FIGURE 36. OUTPUT CHANNEL REGISTER
PHASE SHIFT CONTROL REGISTER
EQUALPHASE
Bit 7 (R/W)
PHASESHIFT6
Bit 6 (R/W)
PHASESHIFT5
Bit 5 (R/W)
PHASESHIFT4
Bit 4 (R/W)
PHASESHIFT3
Bit 3 (R/W)
PHASESHIFT2
Bit 2 (R/W)
PHASESHIFT1
Bit 1 (R/W)
PHASESHIFT0
Bit 0 (R/W)
BIT ASSIGNMENT
EqualPhase
PhaseShift[6..0]
BIT FIELD DEFINITIONS
Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift
is 360/N (where N is the number of channels enabled).
7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq)
In direct PWM modes, phase shift between each channel is PhaseShift<6:0>/12.8MHz
FIGURE 37. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER
23
FN7631.3
August 14, 2012
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